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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD Device
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DS048 (v1.1) February 10, 2000
Product Specification
Features
* * Industry's first TotalCMOSTM SPLD - both CMOS design and process technologies Fast Zero Power (FZPTM) design technique provides ultra-low power and high speed - Static current of less than 75 A - Dynamic current substantially below that of competing devices - Pin-to-pin delay of only 7.5 ns True Zero Power device with no turbo bits or power down schemes Function/JEDEC map compatible with Bipolar, UVCMOS, EECMOS 22V10s Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP) - 24-pin TSOIC-uses 93% less in-system space than a 28-pin PLCC - 24-pin SOIC - 28-pin PLCC with standard JEDEC pinout Available in commercial and industrial operating ranges Advanced 0.5 E2CMOS process 1000 erase/program cycles guaranteed 20 years data retention guaranteed Varied product term distribution with up to 16 product terms per output for complex functions Programmable output polarity Synchronous preset/asynchronous reset capability Security bit prevents unauthorized access Electronic signature for identification Design entry and verification using industry standard CAE tools Reprogrammable using industry standard device programmers
Description
The XCR22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Xilinx offers the XCR22LV10 that offers high speed and low power in a 3V implementation. The XCR22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.
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Functional Description
The XCR22V10 implements logic functions as sum-of-products expressions in a programmable -AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility (Figure 1).
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.
CLK/I0
1 0 0 1 9 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 AR
1 1 0 0 0 1 0 1
24
VCC
DAR SP
Q Q
23
F9
0 1
10
DAR Q Q 1 1 0 0 0 1 0 1
22
F8
20 I1 2 21
SP
0 1 1 1 0 0 0 1 0 1
DAR
33 I2 3 34
SP
Q Q
21
F7
0 1 1 1 0 0 0 1 0 1
DAR SP
Q Q
20
F6
48 I3 4 49
DAR SP Q Q 1 1 0 0 0 1 0 1 0 1
19
F5
65 I4 5 66 Programmable connection.
DAR SP Q Q
0 1 1 1 0 0 0 1 0 1
18
F4
82 I5 6 83
DAR SP Q Q
0 1 1 1 0 0 0 1 0 1
17
F3
97 I6 7 98
DAR Q Q
0 1 1 1 0 0 0 1 0 1
16
F2
110 I7 8 111
SP
0 1 1 1 0 0 0 1 0 1
DAR
121 9 122 130
SP
Q Q
15
F1
I8
0 1 1 1 0 0 0 1 0 1
DAR SP
Q Q
14
F0
I9
10 131 SP
0 1
I10 11 GND 12 NOTE: 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
13
I11
SP00059
Figure 1: XCR22V10 Logic Diagram
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
Architecture Overview
The XCR22V10 architecture is illustrated in Figure. Twelve dedicated inputs and ten I/Os provide up to 22 inputs and ten outputs for creation of logic functions. At the core of the device is a programmable electrically-erasable AND array which drives a fixed-OR array. With this structure, the XCR22V10 can implement up to ten sum-of-products logic expressions. Associated with each of the ten OR functions is an I/O macrocell which can be independently programmed to one of four different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions with either active High or active Low polarity.
44 input lines: * 24 input lines carry the True and Complement of the signals applied to the 12 input pins * 20 additional lines carry the True and Complement values of feedback or input signals from the ten I/Os * 132 product terms: * 120 product terms (arranged in two groups of 8, 10, 12, 14, and 16) used to form logical sums * Ten output enable terms (one for each I/O) * One global synchronous preset product term * One global asynchronous clear product term At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term which is connected to both the True and Complement of an input signal will always be FALSE, and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a Don't Care state exists and that term will always be TRUE.
AND/OR Logic Array
The programmable AND array of the XCR22V10 (shown in the Logic Diagram, Figure 1) is formed by input lines intersecting product terms. The input lines and product terms are used as follows:
CLK/I0 1 11
I1 - I11
PROGRAMMABLE AND ARRAY (44 x
8
10
12
14
16 132)
16
14
12
10
8
RESET
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9 SP00060A
Figure 2: Functional Diagram
Variable Product Term Distribution
The XCR22V10 provides 120 product terms to drive the ten OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic Diagram). This distribution allows optimum use of device resources.
tion of the XCR22V10 to the precise requirements of their designs.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 3 consists of a D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell of the XCR22V10 is determined by the two EEPROM bits controlling these multiplexers. These bits determine output polarity, and output type (registered or non-registered). Equivalent circuits for the macrocell configurations are illustrated in Figure 4.
Programmable I/O Macrocell
The output macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configura3
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PRESET
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
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S1
1 AR D CLK SP Q Q S1 S0 0 1 1 0 0 0 1 0 1 F 0 0 1 1
S0
0 1 0 1
OUTPUT CONFIGURATION
Registered/Active-LOW/Macrocell feedback Registered/Active-HIGH/Macrocell feedback Combinatorial/Active-LOW/Pin feedback Combinatorial/Active-HIGH/Pin feedback
0 = Unprogrammed fuse 1 = Programmed fuse
SP00484
Figure 3: Output Macrocell Logic Diagram
AR D CLK SP Q Q
S0 = 0 S1 = 0 F
S0 = 0 S1 = 1 F
a. Registered/Active-LOW
c. Combinatorial/Active-LOW
AR D CLK SP Q Q
S0 = 1 S1 = 0 F
S0 = 1 S1 F
b. Registered/Active-HIGH
d. Combinatorial/Active-HIGH
SP00376
Figure 4: Output Macrocell Configurations
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD Output Type
The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set High at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset. put of the XCR22V10 will depend on the programmed output polarity. The VCC rise must be monotonic.
Design Security
The XCR22V10 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. Once the security bit is set, it is impossible to verify (read) or program the XCR22V10 until the entire device has first been erased with the bulk-erase function.
Program/Erase Cycles
The XCR22V10 is 100% testable, erases/programs in seconds, and guarantees 1000 program/erase erase cycles.
TotalCMOS Design Technique for Fast Zero Power
Xilinx is the first to offer a TotalCMOS SPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer SPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must accept low performance. Refer to Figure 5 and Table 1 showing the ICC vs. Frequency of our XCR22V10 TotalCMOS SPLD. Table 1: Typical ICC vs. Frequency @ VCC = 5V, 25C Frequency (MHz) 1 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Tupical ICC (mA) 0.5 1.9 3.5 5.0 6.5 8.1 9.5 10.9 12.4 13.9 15.4 16.7 18.1 19.4 20.7 22.1 23.5 24.8 26.2 27.5 28.7
Output Polarity
Each macrocell can be configured to implement active High or active Low logic. Programmable polarity eliminates the need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is driven into the high-impedance state. Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bidirectional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically FALSE and the I/O will function as a dedicated input.
Register Feedback Select
When the I/O macrocell is configured to implement a registered function (S1=0) (Figure 4a or Figure 4b), the feedback signal to the AND array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combinatorial function (S1=1) (Figure 4c or Figure 4d), the feedback signal is taken from the I/O pin. In this case, the pin can be used as a dedicated input, a dedicated output, or a bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a reset condition and the Q output will be low. The actual out-
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
30 TYPICAL 25
20
15 ICC (mA)
10
5
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 SP00486 FREQUENCY (MHz)
Figure 5: Typical ICC vs. Frequency @ VCC = 5V, 25C (10-bit counter)
Absolute Maximum Ratings1
Symbol VCC VI VOUT IIN IOUT TR TJ TSTG ESD
Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied..
Parameter Supply voltage Input voltage Output voltage Input current Output current Allowale thermal rise ambient to junction Maximum junction temperature Storage temperature Static discharge voltage (human body)
2
Min. -0.5 -1.2 -0.5 -30 -100 0 -40 -65 -
Max. 7.0 VCC +0.5 VCC +0.5 30 100 75 150 150 1000
Unit V V V mA mA C C C V
Operating Range
Product Grade Commercial Industrial Temperature 0 to +70C -40 to +85C Voltage 5V 5% 5V 10%
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
DC Electrical Characteristics For Commercial Grade Devices
Commercial: 0C TAMB +70C; 4.75V VCC 5.25V Symbol VIL VIH VI VOL VOH II IOZL ICCQ ICCD1 IOS CIN CCLK CI/O Notes: Parameter Input voltage Low Input voltage High Input clamp voltage Output voltage Low Output voltage High Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current Input pin capacitance Clock input capacitance I/O pin capacitance Test Conditions VCC = 4.75V VCC = 5.25V VCC = 4.75V, IIN = -18 mA VCC = 4.75V, IOL = 8 mA VCC = 4.75V, IOH = -4 mA VIN = 0V to VCC VIN = 0V to VCC VCC = 5.25V, TAMB = 0C VCC = 5.25V, TAMB = 0C at 1 MHz VCC = 5.25V, TAMB = 0C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz Min. 2 -1.2 0.5 2.4 -10 -10 60 1 10 -30 10 10 75 3 15 -100 10 12 10 Typ. Max. 0.8 Unit V V V V V A A A mA mA mA pF pF pF
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1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
AC Electrical Characteristics For Commercial Grade Devices
Commercial: 0C TAMB + 70C; 4.75V VCC 5.25V Symbol Parameter 7 Min. 3 6.75 2 2 15 5 5 5 3 3 20 20 200 103 167 9 9 10 12 143 83 167 10 10 10 12 3 3 20 20 5 5 5 Max. 7.5 Min. 4 8 3 3 15 D Max. 10 Unit ns ns ns ns ns ns ns ns ns s s ns ns MHz MHz MHz ns ns pF pF
tPD Propagation delay time, input or feedback to non-registered output tSU Setup time from input, feedback or SP to Clock tCO Clock to output tCF Clock to feedback1 tH Holt time tAR Asynchronous Reset to registered output tARW Asynchronous Reset width tARR Asynchronous Reset recovery time tSPF Synchronou Preset recovery time tWL Width of Clock Low tWH Width of Clock High tR Input rise time tF Input fall time fMAX1 Maximum FF toggle rate2 (1/tSU + tCF) fMAX2 Maximum internal frequency1 (1/tSU + tCO) fMAX3 Maximum external frequency1 (1/tWL + tWH) tEA Input to output enable tER Input to output disable Capacitance CIN Input pin capacitance COUT Output capacitance
Notes: 1. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected. 2. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
DC Electrical Characteristics For Industrial Grade Devices
Industrial: -40C TAMB +85C; 4.5V VCC 5.5V Symbol VIL VIH VI VOL VOH II IOZL ICCQ ICCD1 IOS CIN CCLK CI/O Notes: Parameter Input voltage Low Input voltage High Input clamp voltage Output voltage Low Output voltage High Input leakage current 3-stated output leakage current Standby current Dynamic current Short circuit output current Input pin capacitance Clock input capacitance I/O pin capacitance Test Conditions VCC = 4.75V VCC = 5.25V VCC = 4.75V, IIN = -18 mA VCC = 4.75V, IOL = 8 mA VCC = 4.75V, IOH = -4 mA VIN = 0V to VCC VIN = 0V to VCC VCC = 5.25V, TAMB = -40C VCC = 5.25V, TAMB = -40C at 1 MHz VCC = 5.25V, TAMB = -40C at 50 MHz One pin at a time for no longer than 1 second TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz TAMB = 25C, f = 1 MHz Min. 2 -1.2 0.5 2.4 -10 -10 70 1 10 -30 10 10 95 3 20 -100 10 12 10 Typ. Max. 0.8 Unit V V V V V A A A mA mA mA pF pF pF
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1. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
AC Electrical Characteristics For Industrial Grade Devices
Industrial: -40C TAMB +85C; 4.5V VCC 5.5V Symbol Parameter Min. 5 8.5 4 03 15 5 5 5 3 3 20 20 111 74 167 11 11 10 12 Max. 10 Unit ns ns ns ns ns ns ns ns ns s s ns ns MHz MHz MHz ns ns pF pF
tPD Propagation delay time, input or feedback to non-registered output tSU Setup time from input, feedback or SP to Clock tCO Clock to output tCF Clock to feedback1 tH Holt time tAR Asynchronous Reset to registered output tARW Asynchronous Reset width tARR Asynchronous Reset recovery time tSPF Synchronou Preset recovery time tWL Width of Clock Low tWH Width of Clock High tR Input rise time tF Input fall time fMAX1 Maximum FF toggle rate2 (1/tSU + tCF) fMAX2 Maximum internal frequency1 (1/tSU + tCO) fMAX3 Maximum external frequency1 (1/tWL + tWH) tEA Input to output enable tER Input to output disable Capacitance CIN Input pin capacitance COUT Output capacitance
Notes:
1. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
2. This parameter measured with a 10-bit, with all outputs enabled and unloaded. Inputs are tied to VCC or ground. This parameter is not 100% tested, but is calculated at initial characterization and at any time the design is modified where current may be affected.
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
Test Load Circuit
VCC +5V S1
C1
C2 I0 F0
R1
DUT
R2
CL
INPUTS In CK Fn OE GND
NOTE: C1 and C2 are to bypass VCC to GND. R1 = 300, R2 = 390, CL = 35pF.
SP00481
Thevenin Equivalent
VL = 2.83V
170
DUT OUTPUT
35 pF
SP00482
Voltage Waveform
+3.0V 90%
10% 0V tR 1.5ns tF 1.5ns
SP00368 MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
Switching Waveforms
INPUT OR FEEDBACK INPUT OR FEEDBACK tPD COMBINATORIAL OUTPUT VT CLOCK
VT
VT tS tH VT tCO
Combinatorial Output
REGISTERED OUTPUT
VT
Registered Output
INPUT tWH tER CLOCK VT OUTPUT tWL
VT tEA VOH - 0.5V VOL + 0.5V VT
Clock Width
Input to Output Disable/Enable
tARW INPUT ASSERTING ASYNCHRONOUS RESET VT tAR REGISTERED OUTPUT VT tARR CLOCK VT REGISTERED OUTPUT CLOCK INPUT ASSERTING SYNCHRONOUS PRESET VT tS tH VT tCO VT tSPR VT
Asynchronous Reset NOTES: 1. VT = 1.5V. 2. Input pulse amplitude 0V to 3.0V. 3. Input rise and fall times 2.0 ns max.
Synchronous Preset
SP00483
"AND" Array: (I,B)
I, B I, B I, B I, B
I, B I, B I, B
I, B I, B I, B
I, B
I, B P, D STATE INACTIVE 1 CODE O STATE TRUE P, D CODE H STATE COMPLEMENT P, D CODE L STATE DON'T CARE P, D CODE -- SP00008
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
Pin Configurations
28-pin PLCC
IO/CLK
Pin Descriptions
Pin Label I1-I11 NC F0-F9 I0/CLK VCC
25 F7 24 F6 23 F5 22 NC 21 F4 20 F3 19 F2
4 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11 12 I9
3
2
1
28
27
26
Description Dedicated input Not Connected Macrocell Input/Output Dedicated Input/Clock Output Supply Voltage Ground
NC
VCC
F9
I2
I1
F8
GND
13 I10
14 GND
15 NC
16 I11
17 F0
18 F1 SP00474
24-pin SOIC and 24-pin TSOIC
IO/CLK I1 I2 I3 I4 I5 I6 I7 I8
1 2 3 4 5 6 7 8 9
24 VCC 23 F9 22 F8 21 F7 20 F6 19 F5 18 F4 17 F3 16 F2 15 F1 14 F0 13 I11 AP00475
I9 10 I10 11 GND 12
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XCR22V10: 5V Zero Power, TotalCMOS, Universal PLD
Ordering Information
Example: XCR22V10 -7 PC 28 C
Device Type Speed Options Temperature Range Number of Pins Package Type
Speed Options -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay
Temperature Range C = Commercial, TA = 0C to +70C I = Industrial, TA = -40C to +85C Packaging Options SO24: 24-pin SOIC VO24: 24-pin TSOIC PC28: 28-pin PLCC
Component Availability
Pins Type Code XCR22V10 24 Plastic SOIC SO24 -10 -7 Plastic Thin SOIC VO24 C, I C 28 Plastic PLCC PC28 C, I C
Revision History
Date 8/4/99 2/10/00 Version # 1.0 1.1 Revision Initial Xilinx release. Convert to Xilinx Format
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